1. Field of the Invention
The present invention generally relates to hardware design and verification. More specifically, the present invention relates to methods and apparatuses for executing a hardware simulation and verification solution.
2. Related Art
Rapid advances in computing technologies have been made possible by advances in design and verification tools because without such tools it would have been almost impossible to design and verify complicated integrated circuits which are commonly found in today's computing devices. Due to the rapidly increasing size and complexity of integrated circuits, there is a strong need to find methods and apparatuses to improve the performance of hardware simulation and verification solutions.
Unfortunately, conventional techniques for improving software performance are not always effective. For example, rewriting the software from scratch so that it can be executed in parallel is impractical due to the enormous costs of rewriting such a complex piece of software. A parallelizing compiler may also fail to improve performance because even the most sophisticated parallelizing compilers often fail to exploit parallelization opportunities in such complex pieces of software. Further, parallelizing only a small portion of the software usually does not substantially improve performance due to Amdahl's law, and partitioning the software into different pieces may degrade performance if the different pieces require large amounts of synchronization.